1. Field of the Invention
The present invention relates to a small area contact region, a high efficiency phase change memory cell and a fabrication method thereof.
2. Description of the Related Art
As is known, phase change memory cells utilize a class of materials that have the unique property of being reversibly switchable from one phase to another with measurable distinct electrical properties associated with each phase. For example, these materials may change between an amorphous disordered phase and a crystalline, or polycrystalline, ordered phase. A material property that may change and provide a signature for each phase is the material resistivity, which is considerably different in the two states.
Specific materials that may be suitably used in phase change cells are alloys of elements of the VI group of the periodic table, such as Te or Se, also called chalcogenides or chalcogenic materials. Therefore, hereinafter, the term “chalcogenic materials” is used to indicate all materials switchable between at least two different phases where they have different electrical properties (resistances) and include thus the elements of the VI group of the periodic table and their alloys.
The presently most promising chalcogenide is an alloy of Ge, Sb and Te (Ge2Sb2Te5) which is already widely used for storing information in overwritable optical disks.
As indicated, for microelectronics applications, the interesting parameter is resistivity that varies of two or more orders of magnitude when the material transforms from the amorphous phase (more resistive) to the crystalline phase (more conductive) and vice versa. Thus a thin film of chalcogenic material may be employed as a programmable resistor, switching between a high and a low resistance condition, with a resistance change ratio higher than 40, as shown in FIG. 1, wherein Vr indicates the read voltage.
Phase change may be obtained by locally increasing the temperature. Under 150° C., both phases are stable. Over 200° C., nucleation of crystallites is fast and if the material is kept to the crystallization temperature for a sufficient time, it changes phase and becomes crystalline. In order to change the phase back to the amorphous state, its temperature is brought over the melting point (about 600° C.) and rapidly cooled.
From an electrical point of view, it is possible to reach both critical temperatures (crystallization and melting temperatures) using an electric current flow through a resistive electrode in contact or close proximity with the chalcogenic material and heating the material by Joule effect.
A chalcogenic element 1 based on the above is shown in FIG. 2, and comprises a resistive electrode 2 and a chalcogenic region 3. The chalcogenic region 3 is generally in the crystalline state to allow good current flow. A portion of the chalcogenic region 3 is in direct contact with the resistive electrodes and forms a phase change portion 4.
By passing an electrical current of suitable value through the resistive electrode 2, it is possible to selectively heat the phase change portion 4 to the crystallization or melting temperatures and cause a phase change.
FIG. 3 shows the plots of the required temperature versus time when a phase change from the crystalline to the amorphous status is desired (curve A) and a phase change from the amorphous to the crystalline status is desired (curve B). Tm indicates the melting temperature and Tx indicates the temperature at which crystallization begins. As shown, amorphization requires a short time (reset pulse) but a high temperature; furthermore the material should be cooled in a very short time (t1) to maintain the atomic disorder and avoid recrystalization of the material. Crystallization requires a longer time t2 (also called set pulse) to allow nucleation and crystal growing.
The state of the chalcogenic material may be read applying a sufficiently small voltage so as not to cause a sensible heating and measuring the current passing through it. Since the current is proportional to the conductance of the chalcogenic material, it is possible to discriminate between the two states.
Of course, the chalcogenic material may be electrically switched between different states intermediate between the amorphous and the crystalline states, thereby giving rise to a multilevel storing capability. In the following however, for sake of clarity, the binary situation will be considered, without the invention being limited thereto.
The possibility of changing the phase from the amorphous to the crystalline state using electrical pulses is indeed not immediately obvious, since, in the amorphous state, the material resistivity is very high and the current flowing through the chalcogenic material would not allow a sufficient dissipation and thus a sufficiently high temperature. However, chalcogenic materials have the property that they change their transport characteristics as a function of the applied electric field. This is shown in FIG. 4, plotting the curve of the current as a function of the voltage for a structure formed by a chalcogenic material arranged between two metal electrodes.
As visible, above a threshold voltage Vth, the structure begins to conduct not following a phase change, but because of a change in the electronic conduction mechanism. This behavior is called “electronic switching”; accordingly, biasing the chalcogenic structure to a voltage higher than the threshold voltage, it is possible to considerably increase the current flow. By causing this current to pass through a suitable neighboring series resistor, that operates as a heater, it is thus possible to obtain, by Joule effect, a sufficient heating of the chalcogenic material up to the crystallization temperature.
The use of the chalcogenic element of FIG. 2 has been already proposed to form a memory cell. To avoid disturbances caused by adjacent memory cells, the chalcogenic element is generally coupled with a selection element, such as a MOS transistor, a bipolar transistor or a diode.
All known approaches however are disadvantageous due to the difficulty of implementing solutions that satisfy present requirements regarding current and voltage withstand capability, functionality, as well as compatibility with current CMOS technologies.
In particular, technological and electrical considerations impose a limit onto the maximum value of the current usable to cause phase change in the memory cells. Indeed, considerations about the present current capability of transistors in a technology with a gate length of 130 nm and a gate oxide withstanding a power supply of 3 V, for memory devices of the present generation (working by 8 or 16 or 32 bits), impose maximum current values of about 100–200 μA that in turn require a contact area between the chalcogenic region and the resistive electrode in the range of preferably, at the most, 20 nm×20 nm. The problem is that such dimensions are far ahead of the present optical (UV) lithography that can hardly reach a linear 100 nm definition.